PRELIMINARY DATA SHEET
256MB Unbuffered DDR SDRAM DIMM
EBD25UC8AKFA-5-E
(32M words
×
64 bits, 1 Rank)
Description
The EBD25UC8AKFA is 32M words
×
64 bits, 1 rank
Double Data Rate (DDR) SDRAM unbuffered module,
mounting 8 pieces of 256M bits DDR SDRAM sealed in
TSOP package.
Read and write operations are
performed at the cross points of the CK and the /CK.
This high-speed data transfer is realized by the 2 bits
prefetch-pipelined architecture. Data strobe (DQS)
both for read and write are available for high speed and
reliable data bus design. By setting extended mode
register, the on-chip Delay Locked Loop (DLL) can be
set enable or disable. This module provides high
density mounting without utilizing surface mount
technology.
Decoupling capacitors are mounted
beside each TSOP on the module board.
Features
•
184-pin socket type dual in line memory module
(DIMM)
PCB height: 31.75mm
Lead pitch: 1.27mm
Lead-free
•
2.5 V power supply
•
Data rate: 400Mbps (max.)
•
2.5 V (SSTL_2 compatible) I/O
•
Double Data Rate architecture; two data transfers per
clock cycle
•
Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
•
Data inputs and outputs are synchronized with DQS
•
4 internal banks for concurrent operation
(Components)
•
DQS is edge aligned with data for READs; center
aligned with data for WRITEs
•
Differential clock inputs (CK and /CK)
•
DLL aligns DQ and DQS transitions with CK
transitions
•
Commands entered on each positive CK edge; data
referenced to both edges of DQS
•
Data mask (DM) for write data
•
Auto precharge option for each burst access
•
Programmable burst length: 2, 4, 8
•
Programmable /CAS latency (CL): 3
•
Programmable output driver strength: normal/weak
•
Refresh cycles: (8192 refresh cycles /64ms)
7.8µs maximum average periodic refresh interval
•
2 variations of refresh
Auto refresh
Self refresh
Document No. E0602E10 (Ver. 1.0)
Date Published October 2004 (K) Japan
URL: http://www.elpida.com
Elpida
Memory, Inc. 2004
EBD25UC8AKFA-5-E
Ordering Information
Data rate
Mbps (max.)
400
Component JEDEC speed bin
(CL-tRCD-tRP)
DDR400B (3-3-3)
DDR400C (3-4-4)
Contact
pad
Mounted devices
EDD2508AKTA-5B-E
EDD2508AKTA-5B/5C-E
Part number
EBD25UC8AKFA-5B-E
EBD25UC8AKFA-5C-E
Package
184-pin DIMM
Gold
(lead-free)
Pin Configurations
Front side
1 pin
52 pin 53 pin
92 pin
93 pin
Back side
144 pin 145 pin 184 pin
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
Pin name
VREF
DQ0
VSS
DQ1
DQS0
DQ2
VDD
DQ3
NC
NC
VSS
DQ8
DQ9
DQS1
VDD
CK1
/CK1
VSS
DQ10
DQ11
CKE0
VDD
DQ16
DQ17
DQS2
VSS
A9
DQ18
A7
Pin No.
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
Pin name
NC
A0
NC
VSS
NC
BA1
DQ32
VDD
DQ33
DQS4
DQ34
VSS
BA0
DQ35
DQ40
VDD
/WE
DQ41
/CAS
VSS
DQS5
DQ42
DQ43
VDD
NC
DQ48
DQ49
VSS
/CK2
Pin No.
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
Pin name
VSS
DQ4
DQ5
VDD
DM0/DQS9
DQ6
DQ7
VSS
NC
NC
NC
VDD
DQ12
DQ13
DM1/DQS10
VDD
DQ14
DQ15
NC
VDD
NC
DQ20
A12
VSS
DQ21
A11
DM2/DQS11
VDD
DQ22
Pin No.
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
Pin name
VSS
NC
A10
NC
VDD
NC
VSS
DQ36
DQ37
VDD
DM4/DQS13
DQ38
DQ39
VSS
DQ44
/RAS
DQ45
VDD
/CS0
NC
DM5/DQS14
VSS
DQ46
DQ47
NC
VDD
DQ52
DQ53
NC
Preliminary Data Sheet E0602E10 (Ver. 1.0)
2
EBD25UC8AKFA-5-E
Pin No.
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Pin name
VDD
DQ19
A5
DQ24
VSS
DQ25
DQS3
A4
VDD
DQ26
DQ27
A2
VSS
A1
NC
NC
VDD
Pin No.
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
Pin name
CK2
VDD
DQS6
DQ50
DQ51
VSS
VDDID
DQ56
DQ57
VDD
DQS7
DQ58
DQ59
VSS
NC
SDA
SCL
Pin No.
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
Pin name
A8
DQ23
VSS
A6
DQ28
DQ29
VDD
DM3/DQS12
A3
DQ30
VSS
DQ31
NC
NC
VDD
CK0
/CK0
Pin No.
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
Pin name
VDD
DM6/DQS15
DQ54
DQ55
VDD
NC
DQ60
DQ61
VSS
DM7/DQS16
DQ62
DQ63
VDD
SA0
SA1
SA2
VDDSPD
Preliminary Data Sheet E0602E10 (Ver. 1.0)
3
EBD25UC8AKFA-5-E
Pin Description
Pin name
A0 to A12
BA0, BA1
DQ0 to DQ63
/RAS
/CAS
/WE
/CS0
CKE0
CK0 to CK2
/CK0 to /CK2
DQS0 to DQS7
DM0 to DM7/DQS9 to DQS16
SCL
SDA
SA0 to SA2
VDD
VDDSPD
VREF
VSS
VDDID
NC
Function
Address input
Row address
Column address
Data input/output
Row address strobe command
Column address strobe command
Write enable
Chip select
Clock enable
Clock input
Differential clock input
Input and output data strobe
Input mask
Clock input for serial PD
Data input/output for serial PD
Serial address input
Power for internal circuit
Power for serial EEPROM
Input reference voltage
Ground
VDD identification flag
No connection
A0 to A12
A0 to A9
Bank select address
Preliminary Data Sheet E0602E10 (Ver. 1.0)
4
EBD25UC8AKFA-5-E
Serial PD Matrix
Byte No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Function described
Number of bytes utilized by module
manufacturer
Total number of bytes in serial PD
device
Memory type
Number of row address
Number of column address
Number of DIMM ranks
Module data width
Module data width continuation
Bit7
1
0
0
0
0
0
0
0
Bit6
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
1
0
0
1
0
1
Bit5 Bit4
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
1
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
1
1
0
0
1
0
0
0
Bit3
0
1
0
1
1
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
Bit2
0
0
1
1
0
0
0
0
1
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
1
1
1
0
0
1
0
0
0
Bit1 Bit0
0
0
1
0
1
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
1
0
0
0
0
0
0
0
Hex value
80H
08H
07H
0DH
0AH
01H
40H
00H
04H
50H
70H
00H
82H
08H
00H
01H
0EH
04H
1CH
01H
02H
20H
C0H
60H
70H
75H
75H
3CH
48H
28H
3CH
48H
28H
40H
Comments
128 bytes
256 bytes
DDR SDRAM
13
10
1
64
0
SSTL2
5.0ns
*1
0.7ns
*1
None.
7.8µs
×
8
None.
1 CLK
2,4,8
4
2, 2.5, 3
0
1
Differential
Clock
VDD ± 0.2V
6.0ns
*1
0.7ns
*1
0.75ns
*1
0.75ns
*1
15ns
18ns
10ns
15ns
18ns
40ns
256M bytes
Voltage interface level of this assembly 0
DDR SDRAM cycle time, CL = 3
SDRAM access from clock (tAC)
DIMM configuration type
Refresh rate/type
Primary SDRAM width
Error checking SDRAM width
SDRAM device attributes:
Minimum clock delay back-to-back
column access
SDRAM device attributes:
Burst length supported
SDRAM device attributes: Number of
banks on SDRAM device
SDRAM device attributes:
/CAS latency
SDRAM device attributes:
/CS latency
SDRAM device attributes:
/WE latency
SDRAM module attributes
SDRAM device attributes: General
Minimum clock cycle time at CL = 2.5
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
Maximum data access time (tAC) from
0
clock at CL = 2.5
Minimum clock cycle time at CL = 2
0
Maximum data access time (tAC) from
0
clock at CL = 2
Minimum row precharge time (tRP)
0
-5B
-5C
0
0
0
0
0
0
Minimum row active to row active
delay (tRRD)
Minimum /RAS to /CAS delay (tRCD)
-5B
-5C
Minimum active to precharge time
(tRAS)
Module rank density
28
29
30
31
Preliminary Data Sheet E0602E10 (Ver. 1.0)
5
